Electrical & Computer Engineering Doctoral Work

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Browsing Electrical & Computer Engineering Doctoral Work by Author "Das, Hritom"

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    Power-Efficient Adaptive Memory Design and Optimization for Video and Deep Learning
    (North Dakota State University, 2020) Das, Hritom
    Memory devices such as Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM) are dominating members of today’s semiconductor industry. Most of the silicon area in a digital system is occupied by memory devices. The video decoder and deep learning are especially constrained by memory devices to process a large amount of data. For example, memory devices are consuming lots of power for video processing. Nowadays, all mobile electronics, such as mobile phones and laptops, are using video data a lot. Due to that, the battery life of mobile devices is highly dependent on power consumption of memory devices. To enhance the battery life of mobile devices, supply voltage can be scaled down. However, memory devices are error prone at low supply voltages. To obtain high quality video, a functionally stable memory design is needed, which means we must provide a higher VDD or use a larger memory cell. As a result, there will be a tradeoff between quality, and silicon area or power consumption. For mobile devices, memory needs to be designed to operate in the sub-threshold region to maximize battery life; however, reducing the supply voltage slows down memory devices, resulting in poor video quality. Hence, memory design is very complicated and time consuming. So, a smart way to design memory devices for a specific application is needed. Mathematical models can be developed to design memory devices based on specific requirements such as silicon area, while optimizing video quality for a target supply voltage. Similarly, optimized memory is needed to better support differentially private deep learning algorithms in local devices. This dissertation first develops a mathematical model for designing optimal memory devices for videos, then develops an optimized memory for differentially private deep learning systems in edge computing devices, and finally develops a run-time adaptable Error Correction Code (ECC) video storage scheme, with minimal area overhead and negligible video quality degradation, in order to significantly reduce power.