Electrical & Computer Engineeringhttps://hdl.handle.net/10365/325572024-03-29T15:08:52Z2024-03-29T15:08:52ZJoint Compression and EncryptionGhosh, Ahanahttps://hdl.handle.net/10365/337312024-03-08T22:06:33Z2010-01-01T00:00:00ZJoint Compression and Encryption
Ghosh, Ahana
This research work proposes two techniques of joint compression and encryption using
Shanon Fano Elias coding and Arithmetic coding respectively. The first scheme proposed
is called Adaptive Shannon-Fano-Elias code where it has been observed that the
complexity of attacks is exponential in m, where m is the length of the string being
compressed. Since mis usually very large (> 220
), the security of our scheme is very high.
The main reason why our scheme's security depends on m is the fact that all attacks require
the ciphertext to be scanned from left to right. The algorithm proposed does not
compromise in the compression ratio produced by normal Shannon Fano Elia coding. The
second scheme proposed uses Arithmetic coding as the compression algorithm as
Arithmetic coding is one of the optimal compression techniques that can be used in various
applications. The algorithm proposed is proved to be secure under an assumption that the
attacker would have access to an algorithm which could decrypt any given message
without the knowledge of the key.
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2010-01-01T00:00:00ZHybrid Renewable Energy System with Wind Turbine and PV PanelsKaderbhai, Munir Shabirhttps://hdl.handle.net/10365/336892024-03-01T17:07:49Z2010-01-01T00:00:00ZHybrid Renewable Energy System with Wind Turbine and PV Panels
Kaderbhai, Munir Shabir
In recent years, there has been increasing concern about the world's heavy
dependence on fossil-based fuels and the pollution caused by such fuels. This has sparked
an increased interest in the use of other renewable sources of energy. In particular,
electricity generation from wind and photovoltaic energy has seen a rapid growth in recent
years. One of the most widely used electric machines used in wind energy conversion
systems is the doubly-fed induction generator (DFIG) which requires a source and power
converter system to feed variable frequency AC voltage to its rotor. Power converter
schemes currently used with DFIGs, however, do not address issues such as the absence
power factor correction in the rectifier (without complicated control loops), soft-switching
in the rectifier, and the possibility of integrating photovoltaic power into the system to
provide rotor injection power.
This thesis presents a hybrid system in which the rotor power can be drawn either
from three-phase AC mains or a photovoltaic (PV) panel-battery combination. While
drawing power from AC mains, an AC-DC converter with soft switching and power factor
correction is used. While supplying rotor injection power from PV panels, one of the
MOSFET switches of the AC-DC converter will be used for boosting the PV panel output
voltage. Various stages of the system are implemented and the details of implementation
and results are discussed for each stage. Suggestions for future research are also offered.
2010-01-01T00:00:00ZVerification of Synchronous Elastic Pipelined SystemsSarker, Koushikhttps://hdl.handle.net/10365/336262024-01-26T15:40:25Z2010-01-01T00:00:00ZVerification of Synchronous Elastic Pipelined Systems
Sarker, Koushik
The constant shrinking of technology has lead to several design challenges that
the synchronous design paradigm is unable to cope with. Elastic design is a novel and
promising design paradigm that overcomes many of these challenges by using
components that are insensitive to the latencies of its inputs.
Verification is a critical problem for any design paradigm. The complexity of
elastic designs arises when the system is pipelined. We develop formal verification
techniques to verify synchronous elastic pipelined systems. Note that the goal of
verification is not to establish the correctness of the algorithm for synthesizing elastic
circuits, but instead, to find bugs and formally prove the correctness of elasticized
designs.
We develop two formal verification procedures. The first procedure checks the
correctness of elastic pipelined systems against their synchronous parent pipelined
systems. The second procedure checks the correctness of elastic pipelined systems
against their high-level non-pipelined specifications (such as an instruction set
architecture). Datatlow through elastic architectures is complicated by the insertion of
any number of elastic buffers in any place in the design. We introduce elastic tokenflow
diagrams, which arc used to track the flow of data in elastic architectures. We
provide a method to construct such diagrams. We also develop highly automated and
systematic procedures based on elastic token-flow diagrams that compute functions that map states of elastic systems to states of their specifications. Such functions, known as
refinement maps, are used to compare behaviors of elastic and synchronous systems and
hence prove their equivalence. We elasticized a 5-stage DLX processor that enables the
insertion of buffers in its data path. We constructed several elastic processors by
introducing up to 5 elastic buffers at various places in the data path and verified
equivalence with both their synchronous parent pipelined systems and also with their
instruction set architecture specifications.
2010-01-01T00:00:00ZPhasor Measurement Unit Placements for Complete Observability using Linear-Time, Quadratic-Time, and Subquadratic-Time HeuristicsSaula, Oluwasijibomihttps://hdl.handle.net/10365/336242024-01-19T18:05:38Z2010-01-01T00:00:00ZPhasor Measurement Unit Placements for Complete Observability using Linear-Time, Quadratic-Time, and Subquadratic-Time Heuristics
Saula, Oluwasijibomi
A phasor measurement unit (PMU) is considered to have the potential to
improve the efficiency of electric power systems by monitoring, control, and protection.
Through measurements of all bus voltages, incoming and outgoing currents, and by
subsequent calculation of all phase angles, employing PMUs on every substation in a
power system will allow complete observation of a power system. However, having a
PMU on every substation may not be economically feasible. Therefore, methodologies
must be devised that can monitor a system with the minimum possible number of
PMUs. In this paper, we propose six graph theoretical PMU placement heuristics.
The proposed heuristics overcome the previous approaches in terms of scalability and
execution time. The proposed heuristics are thoroughly compared and benchmarked
using standard IEEE bus networks ranging from 14 to 300 buses, and a 2,383 bus
system.
2010-01-01T00:00:00Z