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Formal Verification Methodologies for NULL Convention Logic Circuits
(North Dakota State University, 2020)
NULL Convention Logic (NCL) is a Quasi-Delay Insensitive (QDI) asynchronous design paradigm that aims to tackle some of the major problems synchronous designs are facing as the industry trend of increased clock rates and ...
Synthesis of Specifications and Refinement Maps for Real-Time Object Code Verification
(North Dakota State University, 2020)
Formal verification methods have been shown to be very effective in finding corner-case bugs and ensuring the safety of embedded software systems. The use of formal verification requires a specification, which is typically ...
Formal Verification Methodology for Asynchronous Sleep Convention Logic Circuits Based on Equivalence Verification
(North Dakota State University, 2019)
Sleep Convention Logic (SCL) is an emerging ultra-low power Quasi-Delay Insensitive (QDI) asynchronous design paradigm with enormous potential for industrial applications. Design validation is a critical concern before ...
Timed Refinement for Verification of Real-Time Object Code Programs
(North Dakota State University, 2018)
Real-time systems such as medical devices, surgical robots, and microprocessors are safety- critical applications that have hard timing constraint. The correctness of real-time systems is important as the failure may result ...
Formal Modeling and Verification Methodologies for Quasi-Delay Insensitive Asynchronous Circuits
(North Dakota State University, 2019)
Pre-Charge Half Buffers (PCHB) and NULL convention Logic (NCL) are two major commercially successful Quasi-Delay Insensitive (QDI) asynchronous paradigms, which are known for their low-power performance and inherent ...