Equivalence Verification for NULL Convention Logic and Latency-Insensitive Circuits

Abstract

NULL convention logic and latency-insensitive circuits are delay-tolerant circuits that can be synthesized from a synchronous speci cation. These design paradigms can use existing CAD

ows to implement circuits that are robust to process variations and wire delays. Veri cation is an indispensable phase of any commercial design cycle, and needs to be addressed in order to exploit the potential advantages of these design paradigms. Delay-tolerant circuits are of asynchronous nature. Therefore, timing behavior of these delay-tolerant circuits are very disparate from the synchronous speci cations, and verifying equivalence of the synthesized circuit to the synchronous speci cation is one of the main challenges. However, there is no existing work in the literature that address this challenge and still remains an open problem. This study makes an initial e ort in developing equivalence veri cation methods and equivalence checking tools for these design paradigms.