| dc.contributor.author | Wijayasekara, Vidura Manu | |
| dc.description.abstract | NULL convention logic and latency-insensitive circuits are delay-tolerant circuits that can
be synthesized from a synchronous speci cation. These design paradigms can use existing CAD
ows to implement circuits that are robust to process variations and wire delays. Veri cation is an
indispensable phase of any commercial design cycle, and needs to be addressed in order to exploit the
potential advantages of these design paradigms. Delay-tolerant circuits are of asynchronous nature.
Therefore, timing behavior of these delay-tolerant circuits are very disparate from the synchronous
speci cations, and verifying equivalence of the synthesized circuit to the synchronous speci cation
is one of the main challenges. However, there is no existing work in the literature that address
this challenge and still remains an open problem. This study makes an initial e ort in developing
equivalence veri cation methods and equivalence checking tools for these design paradigms. | en_US |
| dc.publisher | North Dakota State University | en_US |
| dc.rights | NDSU Policy 190.6.2 | |
| dc.title | Equivalence Verification for NULL Convention Logic and Latency-Insensitive Circuits | en_US |
| dc.type | Dissertation | en_US |
| dc.type | Video | en_US |
| dc.date.accessioned | 2018-04-17T19:30:38Z | |
| dc.date.available | 2018-04-17T19:30:38Z | |
| dc.date.issued | 2016 | en_US |
| dc.identifier.uri | https://hdl.handle.net/10365/27998 | |
| dc.description.sponsorship | Grants CCF-1117164 and CCF-1242043 | en_US |
| dc.rights.uri | https://www.ndsu.edu/fileadmin/policy/190.pdf | |
| ndsu.degree | Doctor of Philosophy (PhD) | en_US |
| ndsu.college | Engineering | en_US |
| ndsu.department | Electrical and Computer Engineering | en_US |
| ndsu.program | Electrical and Computer Engineering | en_US |
| ndsu.advisor | Srinivasan, Sudarshan K. | |
