Browsing Electrical & Computer Engineering by Subject "equivalence verification"
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Formal Modeling and Verification Methodologies for Quasi-Delay Insensitive Asynchronous Circuits
(North Dakota State University, 2019)Pre-Charge Half Buffers (PCHB) and NULL convention Logic (NCL) are two major commercially successful Quasi-Delay Insensitive (QDI) asynchronous paradigms, which are known for their low-power performance and inherent ... -
Formal Verification Methodology for Asynchronous Sleep Convention Logic Circuits Based on Equivalence Verification
(North Dakota State University, 2019)Sleep Convention Logic (SCL) is an emerging ultra-low power Quasi-Delay Insensitive (QDI) asynchronous design paradigm with enormous potential for industrial applications. Design validation is a critical concern before ...