As a novel non-volatile device, the memristive crossbar array has delivered many promises in giving low computation complexity, high energy efficiency, and high density for neuromorphic computing. However, the intrinsic variability of switching behavior, energy consumption, and stuck at fault are still major obstacles to their implementation. Here we report our investigations of a model that experimentally demonstrates the natural stochasticity of cycle-to-cycle variations. In addition, we propose three techniques to mitigate the adverse impact of cycle-to-cycle variations, optimize energy consumption, reduce system latency, and improve fault tolerance. The relationship of the level of conductance and cycle-to-cycle variation was studied, and experiment results show an optimal number of the levels to mitigate cycle-to-cycle variations in the system. Additionally, the system compresses the number of pulses when the conductance is updated by the pulse stimulus to reduce cycle-to-cycle variations, resulting in a great energy and latency reduction. What’s more, the fault tolerance of the memristor-based system has been improved by a novel weight mapping method. This work paves the way of adopting memristors for more efficient applications in the era of edge computing and the Internet of Things.