The constant shrinking of technology has lead to several design challenges that the synchronous design paradigm is unable to cope with. Elastic design is a novel and promising design paradigm that overcomes many of these challenges by using components that are insensitive to the latencies of its inputs. Verification is a critical problem for any design paradigm. The complexity of elastic designs arises when the system is pipelined. We develop formal verification techniques to verify synchronous elastic pipelined systems. Note that the goal of verification is not to establish the correctness of the algorithm for synthesizing elastic circuits, but instead, to find bugs and formally prove the correctness of elasticized designs. We develop two formal verification procedures. The first procedure checks the correctness of elastic pipelined systems against their synchronous parent pipelined systems. The second procedure checks the correctness of elastic pipelined systems against their high-level non-pipelined specifications (such as an instruction set architecture). Datatlow through elastic architectures is complicated by the insertion of any number of elastic buffers in any place in the design. We introduce elastic tokenflow diagrams, which arc used to track the flow of data in elastic architectures. We provide a method to construct such diagrams. We also develop highly automated and systematic procedures based on elastic token-flow diagrams that compute functions that map states of elastic systems to states of their specifications. Such functions, known as refinement maps, are used to compare behaviors of elastic and synchronous systems and hence prove their equivalence. We elasticized a 5-stage DLX processor that enables the insertion of buffers in its data path. We constructed several elastic processors by introducing up to 5 elastic buffers at various places in the data path and verified equivalence with both their synchronous parent pipelined systems and also with their instruction set architecture specifications.